The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device providing an electro static discharge (ESD) protection element of an open-drain signal terminal in a semiconductor device having the open-drain signal terminal.
In semiconductor devices, the open-drain signal terminal is used for an output terminal, an input terminal or an input/output terminal (hereinafter referred to as a signal terminal) which is expected to apply voltage higher than power source voltage. For a common signal terminal which is not an open-drain type (any one of the output terminal, the input terminal or the input/output terminal), for example, as shown in FIG. 11 of Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-274404, it is common that the ESD protection element (a protection diode and the like) of the signal terminals are provided both of between a power source terminal VDD at a higher voltage side and the signal terminal and between a power source terminal GND in lower voltage side and the signal terminal. However, in the open-drain signal terminal, voltage higher than the voltage of the power source terminal VDD (in the case of an N-channel open drain) is applied or voltage lower than the voltage of the power source terminal GND (in the case of a P-channel open drain) is applied to the signal terminal in a common use state. Therefore, in the case of the N-channel open drain, it is difficult to provide the ESD protection element such as a diode between the signal terminal and the power source VDD at the higher voltage side. Similarly, in the case of the P-channel open drain, it is difficult to provide the ESD protection element between the signal terminal and the power source GND at the lower voltage side. Consequently, an ESD protection of the ESD signal terminal of the open-drain signal terminal needs ESD protection measures different from those for a common signal terminal.
Particularly, in order to reduce power consumption of a semiconductor device when operation of a part of function blocks in all functions is not required depending on operating state of the semiconductor device, control for reducing power consumption has been performed by stopping supply of power source to the function blocks these days. This is because leak current of MOS transistors with forming shorter channel can not be ignored. In this case, supply of power source stops and the power source voltage VDD at the higher voltage side lowers to the power source voltage GND at the lower voltage side. As a result, signal voltage higher than the power source voltage VDD is applied to the signal terminal of the function block. Consequently, the signal terminal is required to employ an N-channel open-drain structure. The ESD protection element which is used between a common signal terminal and the power source terminal VDD cannot be provided between the signal terminal and the power source terminal VDD.
An ESD protection circuit of the open-drain signal terminal used in related arts is shown in FIG. 1. In FIG. 1, 31 is the open-drain signal terminal, 32 being the VDD terminal which is a power source terminal at the higher voltage side, 33 being the GND terminal which is a power source terminal at the lower voltage side, 40 being an input gate, and 34 being an open-drain signal terminal protection element provided between the open-drain signal terminal 31 and the GND terminal 33. The open-drain signal terminal 31 of FIG. 1 is a signal input terminal and provides the input gate 40 which takes a logic level of the open-drain signal terminal 31 into the semiconductor device. The input gate 40 is a CMOS inverter-type input gate including a P-type MOS transistor 41 and an N-type MOS transistor 42.
N-type MOS transistor structure is used in the open-drain signal terminal protection element 34 as a protection element. Since the open-drain signal terminal 31 in FIG. 1 is an input terminal, a gate of the N-type MOS transistor which forms the open-drain signal terminal protection element 34 is fixed at the lower voltage (GND). This open-drain signal terminal protection element 34 functions as a parasitic bipolar transistor (an NPN-type bipolar transistor) when high voltage ESD is applied to the open-drain signal terminal 31 between the open-drain signal terminal 31 and the GND terminal 33, and functions as a protection element by discharging positive charge applied to the open-drain signal terminal 31 to the GND terminal 33.
When the open-drain signal terminal 31 is used as an output terminal, the open-drain signal terminal 31 can function as the output terminal, if conduction or non-conduction of the gate of the N-type MOS transistor forming the open-drain signal terminal protection element 34 is controlled by control signals. When the open-drain signal terminal 31 is only used as an output terminal and is not used as an input terminal, the input gate 40 can be omitted.
When high voltage as ESD is applied to the open-drain signal terminal 31 between the open-drain signal terminal 31 and the VDD terminal 32, a route through which electric current flows to the VDD terminal 32 is shown in FIG. 2. As shown in FIG. 2, a protection element is not directly provided between the open-drain signal terminal 31 and the VDD terminal 32. As a result, charge applied to the open-drain signal terminal 31 is firstly discharged to the GND terminal 33 through the open-drain signal terminal protection element 34 provided between the open-drain signal terminal 31 and the GND terminal 33. Then, the charge is discharged to the VDD terminal 32 through a protection element between the power source terminals 50 provided between the GND terminal 33 and the VDD terminal 32.
Subsequently, although not limited to open-drain signal terminals, a semiconductor device providing an ESD protection structure which can widely be applied is described in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-274404, including a protection for the open-drain signal terminal. FIG. 3A is a plan view showing the ESD protection structure of the semiconductor device, and FIG. 3B is a cross-sectional view taken from line A-A of FIG. 3A. The structure is described with reference to FIGS. 3A and 3B. Over the surface of a P well 101 provided over the surface of a P-type semiconductor substrate 100, a source region 106a, sources and drains of a drain region 107a, a source region 106b, a drain region 107b, and a source region 106c of an N-type MOS transistor are alternatively located along an X direction. Each contact 112 for external connection is provided for each of the source regions 106a to 106c and the drain regions 170a, 170b. Gate electrodes 108 are located sandwiching gate oxide films over the surface of the P-type semiconductor substrate 100 between each of the drain regions 170a, 170b and the source regions 106a to 106c. A P-type guard ring region 110 is provided over the surface of the P well 101 with surrounding all of the source regions 106a to 106c and the drain regions 170a, 170b. A low concentration P-type substrate regions 104 which has lower concentration than the concentration of the P well 101 is provided between the source regions 106a to 106c which are located at both end in the X direction (a direction in which electric current flows to a channel) where all of the source regions 106a to 106c and the drain regions 170a, 170b are alternatively located and the P-type guard ring region 110. An element separation region (an insulating layer) 105 is provided over the surface of a region where an MOS transistor is not provided.
Wirings which are not shown in the view are coupled to the contact 112 provided for each of the source regions 106a to 106c and each of the drain regions 170a, 170b. Interconnections are formed between the sources and between the drains. The N-type source regions 106a to 106c and the P-type guard ring region 110 are coupled to the low voltage power source terminal GND with wirings which are not shown in the view. The drain regions 107, 107b are coupled to a signal terminal with wirings which are not shown in the view. When the N-type MOS transistor is conducted, electric current flows from each of the drain regions 107a, 107b to the source regions 106a to 106c which are adjacently located in the X direction at both sides of the drain regions.
Subsequently, operation when the semiconductor device of FIGS. 3A and 3B which functions as a protection element to the ESD is described. A parasitic bipolar transistor (an NPN-type transistor) formed by the N-type drain regions 107a and 107b as collectors, the P well 101 as a base and the N-type source regions 106a to 106c as emitters is formed between the drain regions 107a, 107b and the source regions 106a to 106c. At the time of common use, both of the P well 101 and the source regions 106a to 106c are coupled to the low voltage power source GND. This parasitic bipolar transistor is not conducted because the P well 101 and the source regions 106a to 106c have the same electric potential. However, when the ESD having higher voltage than the voltage of the low voltage power source terminal GND is applied to the signal terminal, a PN junction between the N-type drain region 107 coupled to the signal terminal and the P well 101 coupled to the low voltage power source GND breaks down. As a result, a certain level of electric current flows between the drain region 107 and the P-type guard ring region 110. When the electric current starts to flow between the drain region 107 and the P-type guard ring region 110, voltage of P well adjacent to the source region 106 increases by resistance of the P well 101. When increase in the electric potential of the P well exceeds 0.6 to 0.7 V which is a threshold value VBE of the parasitic bipolar transistor, the parasitic bipolar transistor starts to conduct and discharge from the drain region 107 to the source region 106 are performed.
When the low concentration P-type substrate region 104 is not provided, P well resistance of the source region 106b located away from the P-type guard ring region 110 is higher than P well resistance of the source regions 106a and 106c located near the P-type guard ring region 110 in P well resistances from the P-type guard ring region 110 to each of the source regions 106a to 106c. Therefore, increase in the source region 106b located away from the P-type guard ring region 110 is higher than the increase in the source regions 106a and 106c located near the P-type guard ring region 110 for voltage elevation of the P well at the time of breakdown of the PN junction diode structure between the drain regions 107a and 107b and the P well 101. At the time of ESD application, a parasitic bipolar transistor formed by an MOS transistor in which a base region is located away from the P-type guard ring region 110 is easy to conduct compared to a parasitic bipolar transistor in which the base region is located near the P-type guard ring region 110. Consequently, the parasitic bipolar transistor in which the base region is located near the P-type guard ring region 110 may not function well as a protection element.
In Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-274404, even a parasitic bipolar transistor located near the P-type guard ring region 110 sufficiently functions as a protection element in such a way that each MOS transistor provided as the protection element by increasing P well resistance at the time of ESD application is almost simultaneously triggered as the parasitic bipolar transistor. This is achieved by providing the low concentration P-type substrate region 104 between the MOS transistor located near the P-type guard ring region 110 and the P-type guard ring region 110.
In an ESD protection structure in which multiple protection elements are provided in parallel, it is known that a structure in which each ballast resistance is provided in series between each protection element and terminal so as to simultaneously operate each protection element in parallel as the protection elements without concentrating electric current only in a part of the protection elements and each protection element simultaneously operates in parallel is effective. FIG. 4 is a perspective view showing a part of a structure of a semiconductor device which provides an improved ballast resistance structure described in Japanese Unexamined Patent Application Publication No. 2005-183661. In FIG. 4, a P well 26 is provided over the surface of a silicon substrate 2 and a source region 6 and a drain region 14 of an N-type MOS transistor 23 are provided over the surface of the P well 26. The drain region 14 is coupled to an N+-type diffusion region 15 through a contact 18, a metal wiring 20 and a contact 19. Another contact 21 is further provided over the N+-type diffusion region 15 and coupled to a metal wiring 22. The metal wiring 22 is coupled to a pad which is not shown in the view. The drain region 14 and the N+-type diffusion region 15 are insulated by a STI region 5. The drain region 14, the N+-type diffusion region 15 and the STI region 5 form a ballast resistance region 7 as a whole. In Japanese Unexamined Patent Application Publication No. 2005-183661, by this ballast resistance region 7, the ballast resistance having sufficient resistance value is realized in small increase in area by coupling to the pad from the drain region 14 through the contact 18, the metal wiring 20, the contact 19, the N+-type diffusion region 15, the contact 21 and the metal wiring 22.
In Japanese Unexamined Patent Application Publication No. 2009-71173, a semiconductor device providing an ESD protection element which complements a protection diode formed by a drain of an MOS transistor and a P-type guard ring and intends to obtain sufficient discharge capacity is described. This semiconductor device is prepared by providing an N-type cathode region, which is located over the surface of the P well existing inside of the P-type guard ring region surrounding the N-type MOS transistor provided over the P well, and is coupled to a signal terminal more adjacent to the P-type guard ring than the drain of the N-type MOS transistor coupled to the signal terminal.